The present disclosure relates to a Duty Cycle Correction (DCC) circuit and a Delayed Locked Loop (DLL) circuit using the same, and more particularly to a DCC circuit for preventing an internal clock signal, in which a variation of internal delay elements created by an external factor (e.g., a power-supply voltage variation) is insufficiently reflected, from being generated, and a DLL circuit using the DCC circuit.
With the increasing degree of integration of a semiconductor memory, the semiconductor memory has been continuously improved to enhance its operation speed. In order to enhance the operation speed of the semiconductor memory, a synchronous memory device capable of being synchronized with a clock signal received from an external part of a memory chip has been recently introduced to the market.
However, if the above-mentioned synchronous memory synchronizes its data with the external clock signal, and outputs the synchronized result, an unexpected delay of “tAC” (output data Access time from Clk) occurs, and the number of valid data windows is reduced, such that an unexpected faulty operation occurs in the synchronous memory which is operating at high frequency. Therefore, in order to allow data to be correctly synchronized with a rising edge or a falling edge of the clock signal, a DLL circuit has been recently developed. The DLL circuit generates a DLL clock signal capable of delaying the external clock signal by a predetermined period denoted by “tCK-tAC”, such that the data can be correctly synchronized with the rising-or falling-edge of the clock signal.
The above-mentioned DLL circuit generates an internal clock signal for compensating for internal delay elements of a DRAM by an external clock signal, and this operation of the DLL circuit is generally called a locking process.
FIG. 1A shows a block diagram illustrating a conventional DLL circuit 100.
Referring to FIG. 1A, the DLL circuit 100 is designed to perform a DCC (Duty Cycle Correction) operation. The DLL circuit 100 includes a clock buffer 110, a first/second DLL unit 120, a DCC unit 130, and a drive 140.
The DCC unit 130 includes a clock input unit 131. FIG. 1B is a conceptual diagram illustrating the clock input unit 131. Referring to FIG. 1B, the clock input unit 131 delays a first clock input signal (clk_r) by a predetermined period using a first delay 132, and generates a first internal clock signal (RCLK). The clock input unit 131 delays a second clock input signal (clk_f) by a predetermined period using a second delay 133, and generates a second internal clock signal (FCLK).
The above-mentioned DLL circuit 100 compares a phase of a reference clock signal (Ref clk) with a phase of a feedback clock signal (feedback clk). If a phase difference between the reference clock (Ref clk) and the feedback clock signal (feedback clk) is equal to or less than a predetermined delay period, it is determined that the locking occurs in the DLL unit 120. In this case, in order to reduce an amount of current consumption at the DLL unit 120, the second DLL 122 for generating the second clock input signal (clk_f) is switched off.
Under the above-mentioned situation, if a power-supply voltage is abruptly changed, an unexpected variation occurs in the DRAM intern al delay element, such that the locking of the DLL unit 120 is broken. If the locking state of the DLL unit 120 is broken, the first DLL 121 of the ON state recovers the locking state by an update process, and generates the first clock input signal (clk_r) in which the above-mentioned DRAM internal delay element's variation is reflected. However, the second DLL 122 of the OFF state does not recover the locking state, such that the second DLL 122 generates the second clock input signal (clk_f) in which the DRAM internal delay element's variation is not reflected.
As a result, the above-mentioned DLL circuit must unavoidably synchronize data with a DLL clock signal created by the second internal clock signal (FCLK) in which the internal delay element is insufficiently reflected, such that it unavoidably increases the delay time denoted by “tAC” (output data Access time from Clk).